Question 1

What is Silicore EDA Lab?

Accepted Answer

An online lab by Broadmate Global for writing, compiling and simulating Verilog, SystemVerilog and UVM in the browser. It runs the open-source Verilator 5.054 and Icarus Verilog 12 simulators and shows the waveform and coverage the simulator produced.

Question 2

Does Silicore support UVM?

Accepted Answer

Yes. The Accellera uvm-core 2020.3.1 library is compiled with Verilator. Tests are selected with +UVM_TESTNAME and PASS or FAIL comes from the UVM report summary. It is built without DPI, so regex config lookups and HDL backdoor access are not available.

Question 3

Is Silicore EDA Lab free?

Accepted Answer

Yes. Sign-up is open and free; each account has daily limits on the number of runs.

Question 4

Can I use Silicore on my own website or platform?

Accepted Answer

Yes. There is a REST API with asynchronous jobs, API keys and short-lived browser tokens, an iframe editor that only your allowed origins can embed, and a dependency-free JavaScript SDK.

Question 5

Is it compatible with Questa, ModelSim or VCS?

Accepted Answer

No. Silicore runs open-source engines. Standard Verilog, most SystemVerilog and UVM work, but designs that rely on vendor-specific features may need changes.